As the clock rates of computer system interconnect busses increase in order to generate greater system performance, signal integrity issues become more important. An example of a typical signal integrity issue is illustrated in FIG. 1. An input voltage 115 typifies a voltage as seen at a receiving device on a high speed bus. For this example, the input voltage 115 is considered in a logically high state when above a reference voltage 110. The input voltage 115 is considered in a logically low state when below the reference voltage 110. The input voltage 115 is making a transition from the logically low state to the logically high state.
However, as can be seen in the figure, the waveform for the input voltage 115 does not make a smooth transition from the logically low state to the logically high state. The distortion is due to reflections, or ringback, on the transmission line carrying the input voltage 115. The particular distortion displayed in this example poses a particular problem in that the waveform dips below the reference voltage 110 after first crossing the reference voltage from low to high at time A. If the receiving device were to sample the input voltage when the input voltage dips below the reference voltage 115, the receiving device would see a logically low voltage level instead of the intended logically high voltage level.
One technique for solving the ringback problem described above is to not allow the receiving device to sample the input voltage 115 until the input voltage 115 crosses the reference voltage from low to high at time C at the earliest. This can be accomplished by selecting a system clock period that is long enough to allow the input voltage waveform to settle before the receiving device samples the input voltage 115. By waiting until the ringback condition settles before sampling, the receiving device can be assured that the input voltage 115 is in the proper state. However, this technique has a drawback in that by elongating the clock period, system performance is degraded. In the absence of ringback, the clock period would be set so that the receiving device would sample the input voltage as soon as the input voltage 115 made its first low to high transition across the reference voltage 110 at time A.
An alternative to elongating the clock period is reducing the distance the input voltage 115 must travel between the transmitting device and the receiving device. This alternative places difficult restrictions on motherboard manufacturers as it becomes increasingly difficult to manufacture motherboards when very short signal trace lengths are required.
Another technique that may be used to try to solve the ringback problem is to use a Schmitt trigger on the input signal. For this example, a Schmitt trigger will allow the receiving device to see a logically high voltage level once the input voltage 115 crosses a Schmitt trigger level 120 at time B. While the Schmitt trigger solution allows a reduction in clock period equal to the time interval between points B and C, the Schmitt trigger solution still has the disadvantage of requiring the receiving device to wait until at least time B before sampling the input voltage 115. Therefore, the clock period must be increased by an amount of time equal to the period between time A and time B over the ideal case in order to allow the input voltage 115 time to reach the Schmitt trigger level 120 and to ensure that the receiving device will sample a valid input voltage state.